The present invention relates generally to semiconductor manufacturing, and more particularly to, a process for forming features on a semiconductor wafer using a SCattered Angular Limited Projection E-Beam Lithography (SCALPEL) process.
One goal in modern semiconductor fabrication is to improve the density of active elements provided on a single semiconductor die, thus increasing the number of die per wafer. As is known in the art, very large scale integration (VLSI) has evolved into ultra-high large scale integration (ULSI) where tens or hundreds of millions of active elements and devices are placed into a single integrated circuit (IC) die. This density is obtained by currently making devices that have a smallest-possible physical device dimension (i.e., critical dimension (CD)) on the order of 0.18 micron. In order to continue to improve this density without significantly increasing die size, and more importantly, to continue to improve device speed, there is a desire to further decrease the critical dimensions (CDs) of active elements and other devices on the semiconductor die beyond 0.18 micron.
Lithographic techniques are typically used in the formation of multi-level circuits on a semiconductor die. Currently, lithographic techniques take advantage of i-line (365 nanometer) and deep ultra-violet (DUV, 248 nanometer) energy sources to make 0.25 to 0.18 micron device dimensions. By decreasing wavelength of the energy utilized in these lithographic techniques, smaller active elements and transistors may be realized by enabling the creation of smaller critical dimensions (CDs). Accordingly, smaller wavelength, higher energy sources have been investigated for lithographic use in the IC industry, including deep ultra-violet (DUV) (193 nanometers), extreme ultra violet (EUV), approximately 11.0 to 13.4 nanometers), and X-ray sources.
Another lithographic technique, projection electron beam lithography (EBL), shows potential in meeting the future needs of the IC industry, including increased throughput and fine critical dimension (CD) control. In general, a projection electron-beam lithography system scans a beam at extremely high speeds across a masked surface to create an image on a semiconductor device. Electron optics can be inserted in the E-beam path to provide a means of advantageous image reduction. One specific type of projection electron beam lithography is known as SCattering with Angular Limitation in Projection Electron-Beam Lithography (SCALPEL). The basic principles of the SCALPEL technique are illustrated in prior art FIG. 1.
Turning to FIG. 1, the basic principles of SCALPEL are illustrated. As shown, a mask 10 having a patterned scattering layer 14 is provided on membrane 12, through which an electron beam (E-beam) is projected as represented by the arrows at the far left of FIG. 1. Particularly, the patterned scattering layer 14 contains material having a higher atomic number than that of the membrane 12. The scattering effect of the electron beam through portions of the mask is illustrated in FIG. 1 between membrane 12 and a lens 20. As shown, those portions of the electron beam that pass through the scattering layer 14 tend to be scattered to a greater extent as compared with those portions of the E-beam that pass through the membrane material having no overlying scattering layer 14.
In FIG. 1, the electron beam passes through the mask 10 and is focused through an electron focusing system, represented by lens 20. The electron beam (E-beam) then passes through back focal plane filter 30. The filter 30 has an aperture that is provided to permit passage of those portions of the electron beam that were not scattered by the scattering layer of the mask 10. In other words, beams that were scattered at or greater than some finite threshold angle are not passed through the filter 30 while all beams having a scattering angle at less than the some finite threshold angle are passed by the filter 30. The portion of the electron beam passing through the filter 30 is then projected onto a semiconductor wafer 40 having a plurality of die 42 and a resist layer 44 formed thereon. The resist layer is formed by conventional techniques such as by spin coating and baking processes.
The electron beam forms an image in the photoresist of the wafer 40. The image includes areas of high exposure intensity formed by those portions of the electron beam that pass between patterned portions 14 of the mask 10, and areas of relatively low exposure intensity formed by those portions of the electron beam that pass through the patterned areas 14 of the mask 10. Therefore, via a light scattering technique, a high-resolution image may be projected onto the resist layer 44, which is then developed to form a patterned resist layer 44 as shown in FIG. 1. Thereafter, the material exposed through the patterned resist layer may be etched or developed using an appropriate etchant. It is noted that the power of the system may be adjusted so as to provide a 3-5xc3x97 reduction in image size, typically 4xc3x97 is a common image reduction size.
Turning to FIG. 2, a top perspective plan view of the mask 10 of FIG. 1 is illustrated. Mask 10 illustrates four adjacent windows, where one window is labeled as window 50. It is noted that typically an array of windows, such as a 8-by-60 array of windows, are formed on a wafer where many more than just the four representative windows in FIG. 2 are formed on the mask 10. In essence, only four windows 50 in FIG. 4 are provided in FIG. 2 for ease of illustration. Each window 50 includes a data field region 52 bounded by a skirt region 54. As illustrated, a plurality of patterned features 48, which make up the scattering layer 14 are formed within the data field region 52. During patterning, exposure of the windows 50 is xe2x80x9csteppedxe2x80x9d over a surface of a semiconductor device in X-Y location increments, so as to form a contiguous pattern 60, as illustrated in FIG. 3. Each of the windows 50 is butted or stitched together via fine lithographic alignments such that the contiguous pattern 60 is formed from the segmented mask windows 50 of FIG. 2. In this regard, the separated windows in FIG. 2 are slightly overlapped with each other as indicated by the dotted lines 58 in FIG. 3 in order to form the contiguous pattern on the wafer. The overlapping of the windows 50 during exposure forms first overlap region 58a and second overlap region 58b which intersect each other at multiple overlap region 50c. 
Along first overlap region 58a, and along second overlap region 58b, the semiconductor device is subjected to energy exposure two times or 2xc3x97 the typical exposure. Along multiple overlap region 50c, the semiconductor wafer is exposed to the electron beam four times and therefore receives 4xc3x97 the normal exposure due to overlapping of windows 50 during E-beam exposure.
The present inventor has recognized that multiple exposures along overlap regions 58a-58b and 50c are problematic. Particularly, as is understood in the art, the materials provided for formation of the scattering layer 14 to form the patterned features 48 is effective to provide an image contrast on the order of 5 to 6. In other words, the portions of the semiconductor device corresponding to the patterned features 48 receive ⅕th to ⅙th the intensity of the electron beam as compared to unpatterned regions or unmasked portions of the mask 10. According, exposure at multiple overlap region 50c becomes problematic, since multiple overlap region 50c receives a ⅕th dose of electrons four times (4xc3x97), which tends to result in an unwanted definition of a feature on the substrate in this multiple overlap region 50c. 
A further problem with this prior art process is illustrated in connection with FIG. 4. As illustrated, window 50 includes first and second patterned features 48, each of which are relatively large and positioned in close proximity to each other as is common in the IC art. As is understood, the electron beam is exposed along patterned features 48 as previously discussed with respect to FIG. 1. Electrons are scattered by the material on mask 50 to different degrees thereby forming features 48 on the wafer. Electrons may be scattered to such an extent that scattering around the edges of the regions 48 causes an uneven exposure or graded exposure of the photoresist around the edges of mask regions 48 as shown in FIG. 4. Thus, in the case of relatively large features, a relatively large number of electrons are being scattered, which may lead to proximity errors arising or significant energy exposure to occur between the features where such exposure is not desired.
As illustrated in FIG. 4, the proximity error is illustrated by the thin separation region lying between the features 48. Typically, the photoresist is chemically developed where resist regions that are exposed at a level greater than D0 is removed while the resist regions that are exposed at a level less than D0 remains on the wafer (or vice versa). Therefore, where the quantum of exposure is above dose D0, which is the minimum dose to complete exposure of the photoresist, a pattern is formed. Accordingly, the features may not be accurately written onto the semiconductor device, and may overlap or bleed into each other, thereby causing electrical short circuits or adversely altering critical device dimensions (CDs) where the regions 48 are either shorted to each other as in FIG. 4 or at least have improper physical dimensions on the wafer.
Accordingly, it is quite clear that a need exists in the art for an improved method of forming a semiconductor device utilizing SCALPEL technology, particularly a technique and a mask therefor that overcome the proximity errors described above in connection with FIG. 4, as well as the exposure errors in connection with FIGS. 2 and 3 described above.